it doesn't look all that useful, it just puts more detailed information about the top failing path into the TimeQuest report that gets output to the console during compilation
with switch OFF:
Info (332146): Worst-case minimum pulse width slack is -0.146
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -0.146 -10.364 clk
with switch ON:
Info (332115):
Info (332113): Report Minimum Pulse Width: Found 1 results (1 violated). Worst case slack is -0.146
Info (332113): Targets: [get_clocks {clk}]
Info (332113): -nworst: 1
Info (332113): -detail: full_path
Info (332113): Path# 1: slack is -0.146 (VIOLATED)
Info (332113): ===================================================================
Info (332113): Node : divider_r[0]
Info (332113): Clock : clk
Info (332113): Type : Low Pulse Width
Info (332113):
Info (332113): Late Clock Arrival Path:
Info (332113):
Info (332113): Total (ns) Incr (ns) Type Element
Info (332113): ========== ========= == ==== ===================================
Info (332113): 0.500 0.500 launch edge time
Info (332113): 0.500 0.000 source latency
Info (332113): 0.500 0.000 clk
Info (332113): 0.500 0.000 FF IC clk~input|i
Info (332113): 1.093 0.593 FF CELL clk~input|o
Info (332113): 1.372 0.279 FF IC clk~inputclkctrl|inclk
Info (332113): 1.481 0.109 FF CELL clk~inputclkctrl|outclk
Info (332113): 2.597 1.116 FF IC divider_r[0]|clk
Info (332113): 2.711 0.114 FF CELL divider_r[0]
Info (332113):
Info (332113): Early Clock Arrival Path:
Info (332113):
Info (332113): Total (ns) Incr (ns) Type Element
Info (332113): ========== ========= == ==== ===================================
Info (332113): 1.000 1.000 launch edge time
Info (332113): 1.000 0.000 source latency
Info (332113): 1.000 0.000 clk
Info (332113): 1.000 0.000 RR IC clk~input|i
Info (332113): 1.299 0.299 RR CELL clk~input|o
Info (332113): 1.563 0.264 RR IC clk~inputclkctrl|inclk
Info (332113): 1.666 0.103 RR CELL clk~inputclkctrl|outclk
Info (332113): 2.769 1.103 RR IC divider_r[0]|clk
Info (332113): 2.846 0.077 RR CELL divider_r[0]
Info (332113): 2.898 0.052 clock pessimism
Info (332113):
Info (332113): Required Width : 0.333
Info (332113): Actual Width : 0.187
Info (332113): Slack : -0.146 (VIOLATED)
Info (332113): ===================================================================
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