Quartus 12_Analysis and Synthesis Failed_Help

Your code requires memory access in two separate processes, one for write and one for read.

This possibly implies the compiler can't infer a simple synchronous ram, and it could implement far more logic than what is actually required. Probably it implements a dual port ram or it infers latched to cover all data paths.

Please follow the guidelines in this document for inferring ram functions:

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf (read from page 14)