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Altera_Forum
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14 years ago

Quartus 10.0 complains of nested clock gating scheme

Hi, I replace the asic clock gating cell with ALTCLKCTRL module when I run quartus 10.0 to build SOF file. However, the process stops because the input clock of ALTCLKCTRL module is another ALT...
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Altera_Forum
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14 years ago

Hi Rbugalho,

It seems "fitting to optimize all paths for hold timing" works!!

I can get EJTAG connected now.

However, it looks like a side-effect that I can't access to DRAM on the FPGA board any more. The dram clock is derived from fpga_pll (a megafunction, clock ratio is XTAIL*9/2 where XTAIL is a clock source from PAD) and I didn't set any constraint on it.

I think dram access problem is a timing issue so here comes a few questions about timing:

a. should I use create_clk command on the dram clock?

b. how to get timing report of clocks derived from fpga_pll?

c. do I have to set any constraint or options for dram clock at this situation? (I mean, with the option fix hold time for ALL PATH)

Thanks,

Acme