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Altera_Forum's avatar
Altera_Forum
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14 years ago

Quartus 10.0 complains of nested clock gating scheme

Hi, I replace the asic clock gating cell with ALTCLKCTRL module when I run quartus 10.0 to build SOF file. However, the process stops because the input clock of ALTCLKCTRL module is another ALT...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

By custom, I mean this.

The FPGA has a dedicated JTAG interface, which can be used to configure the FPGA, for SignalTap, etc, etc.

If I understand you correctly, you are using the FPGA to protype a CPU, which happens to have it's own JTAG interface as well.

Nothing wrong with that, I'm just trying to get situated here.

By the way, why "-add" on the create_clock constrain?