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Altera_Forum
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14 years ago

Quartus 10.0 complains of nested clock gating scheme

Hi, I replace the asic clock gating cell with ALTCLKCTRL module when I run quartus 10.0 to build SOF file. However, the process stops because the input clock of ALTCLKCTRL module is another ALT...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Uh...i am not quite sure the JTAG interface is a custom JTAG interface or not.

I mean there is only one EJTEG interface on the fpga(820) mainboard and we get trace32 or similar device connected to it.

The EJTAG related PADs will directly connect to those on the interface of internal CPU.

After tracing some posts of "Auto Gated Clock Conversion", it seems it is not easy to get it work .....but, i will turn it on and give it a try.

BTW, I have ever tried "fitting to optimize all paths for hold timing" once and it takes more than 24 hours and can't get finished while original process without the option just takes about 5 hours.

So....okay I will try it again with both new options.

("synthesis optimization technique for speed" is my default setting)

Thanks,

Acme