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Altera_Forum
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14 years ago

Quartus 10.0 complains of nested clock gating scheme

Hi, I replace the asic clock gating cell with ALTCLKCTRL module when I run quartus 10.0 to build SOF file. However, the process stops because the input clock of ALTCLKCTRL module is another ALT...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

As I said, Quartus has an option ("Auto Gated Clock Conversion") to automatically replace gated clocks with clock enables during synthesis.

Try it.

I assume that JTAG interface is a custom JTAG interface in your design, not the FPGA's JTAG interface.

You can try and fidle with some of the synthesis and fitting options.:

- Set synthesis optimization technique for speed.

- Set fitting to optimize all paths for hold timing.