Quartus 10.0 complains of nested clock gating scheme

Thank Kbugalho and Kaz for the explanation of clock enable concept.

It reminds me that the coding style of "clock enable" will be transfered into ICG cell in netlist (when synthesizing with some options as I know).

It is also a kind of power saving scheme.

However, this can not solve my problem.

It is impossible for me to modify the RTL code of the soft IP into clock enable style.

My biggest problem based on the pure quartus flow is that JTAG connection is failed. The CPU function seems to work well according to signal tap waveform. I have the following constraint related to EJ_CLK:

create_clock -name {PAD_EJ_TCK} -period 25.000 -waveform { 0.000 12.500 } [get_ports { PAD_EJ_TCK }] -add

Besides, below is related setting in qsf file:

set_instance_assignment -name FAST_INPUT_REGISTER ON -to PAD_EJ_TCK

set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to PAD_EJ_TCK

set_global_assignment -name FMAX_REQUIREMENT "40 MHz" -section_id clk_ejtag

set_instance_assignment -name CLOCK_SETTINGS clk_ejtag -to PAD_EJ_TCK

And the timing report shows as below:

-Slow 900mV 85C Model Setup Summary PAD_EJ_TCK -3.609

-Slow 900mV 85C Model Hold Summary PAD_EJ_TCK -1.327

I think the bad timing is the problem that JTAG can't be connected well.

Do you have any idea of this?

What esle I can set to fix timing violations?

Is path constraint helpful? Would you give me an example?

Thanks,

Acme