Quartus 10.0 complains of nested clock gating scheme

Each ALTCLKCTRL block sits at the top of a clock distribution tree, which can only be fed by dedicated clock input pins, PLLs or logic.

Thus, two of them can't be chained together directly. It should be possible to chain two of them by placing a LCELL primitive bewteen them. But this will lead to the clock skew issues one is trying to avoid.

One solution would be to rethink your clock trees and gating logic, so that you no longer need to cascade ALTCLKCTRL blocks.

These are Quartus style guideline for implementing clock gating with logic:

http://quartushelp.altera.com/10.1/mergedprojects/verify/da/comp_file_rules_clock.htm

Implementing will also lead to clock skew issues. However, Quartus has an option to try to convert gated clocks (following the above style) into clock enables.

Never tried it, though!

Implementing clock enables manually is simple, but it requires code changes. All you need to do is to follow the template:

always @ (posedge clk, posedge reset)

begin

if (reset) begin

// Active high reset stuff

end

else if (enable) begin

// logic goes here

end

end