Quartus 10.0 complains of nested clock gating scheme

As I said I am no expert on ASIC to FPGA rules but I have gut feeling that replacing clock cells with altclkctrl may not be that straight forward.

You will need to identify the clocking plan of your ASIC design then emulate same plan from PLLs (this is easy) and if necessary use clock enable in any clock domain as needed.

The clock enable signal is generated from ordinary logic but using the clock of given domain. For example a counter can be used to generate pulses to enable a clocked register or freeze it. In theory from a single clock you can generate any rate below clock be it integer or fractional.

In RTL you just clock the process as usual then add if construct immediately after clock edge ...if clk_en then ....... end

so that every register is switched under your control in any given process. However, there are some logic pitfalls in interfaces between modules.

For fractional rate generation I commonly use accumulator that adds up n modulo m to generate n/m * clock rate. Though not regular but correct for processing digits