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Altera_Forum
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14 years ago

Quartus 10.0 complains of nested clock gating scheme

Hi, I replace the asic clock gating cell with ALTCLKCTRL module when I run quartus 10.0 to build SOF file. However, the process stops because the input clock of ALTCLKCTRL module is another ALT...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Thank Kaz for the prompt response.

I have traced some discussions about the "clock gating" issues here and I heard a lot of suggestions like "using clock enable to replace some clocks".

I am sorry that I didn't look into the idea carefully.

Would you mind giving me a brief explanation(or a link) or better an example of that?

(It seems the concept is very basic so that people don't explain it anymore)

In fact, the nested clock gating scheme is from a soft IP and the clock path is a bit complicated. I don't really want to make any modifications on it even in FPGA mode.

All I can do is to replace the clock gating module.......

BTW, it seems Synplify tool can recognize the RTL coding style as in my previous post and nested clock gating scheme is not a problem at all.

I am wondering if I need to turn on some sort of settings/options in qsf file to get Quartus understand what I wanna do.

Thanks,

Acme