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Honored Contributor

14 years ago

Quartus 10.0 complains of nested clock gating scheme

Hi, I replace the asic clock gating cell with ALTCLKCTRL module when I run quartus 10.0 to build SOF file. However, the process stops because the input clock of ALTCLKCTRL module is another ALT...

Altera_Forum

Honored Contributor

14 years ago

I am not expert of ASIC to FPGA migration but I think it is not standardised.

You better plan to regenerate your clocks from PLLs and only mux them if absolutely necessary.

Have you considered using clock enable to replace some clocks?

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Quartus 10.0 complains of nested clock gating scheme

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