Quartus : Master clock could not be derived

Thank you for sharing the files ,

Reason I requested for the file that I assumed you already done the constraint manually and getting the this warning. Hence I am curious to know what is going on :) ..

Anyway I noticed you didnt add constraint ,Can you create .sdc file (Add to the project) and add below commands to it . Once I added , those warning went off

derive_pll_clocks -create_base_clocks

derive_clock_uncertainty

create_clock -period 10.000 -name refclk1 -waveform {0 5} [get_ports {clk_ffly0_ref}]

Also Noticed your top module of VHDL is incomplete . (i.e) VHDL based RTL must add the component port and port mapping of those component .

Attached modified top module file for reference.

Thank you,

Regards,

Sree

I think "derive_pll_clocks" command is obsolete (with quartus 18.1 pro and stratix 10)

But sorry I wasn't clear : It's just about understanding why, not about solving a concrete case.

My question is exactly on why do I have to define the clk_ffly0_ref for the pll_40 and I don't have to do it for the refclk_100 in the pll_gen. It doesn't seem logic to me.

Since all my clocks are part of a PLL, it should not be necessary to declare any clock (I mean create_clock or create generated clock commands).

Thanks in advance