library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library LASP_ip;
use LASP_ip.LASP_ip_comp.all;

entity fmc_test is
port(
                clk_ffly0_ref        : in std_logic;
		refclk_100           : in std_logic;
		user_led_r				: out std_logic_vector (3 downto 0):="0000";
		fmca_la_tx_p         : out std_logic_vector (16 downto 0):="00000000000000000"
);
end entity;

architecture behavior of fmc_test is 
signal clk_40   :std_logic;
signal clk_40s  :std_logic;
signal clk_320  :std_logic;
signal lock_s   :std_logic;
signal lock2_s  :std_logic;

--begin

component PLL_40
port (
	rst :in std_logic;      --//   reset.reset
	refclk :in std_logic;   --//  refclk.clk
		locked :out std_logic;--   //  locked.export
		outclk_0 :out std_logic-- // outclk0.clk
	);
end component ;

component PLL_gen
port (
		rst :in std_logic;      --//   reset.reset
		refclk :in std_logic;   --//  refclk.clk
		locked :out std_logic;   --//  locked.export
		outclk_0 :out std_logic; --// outclk0.clk
		outclk_1 :out std_logic --// outclk1.clk
	);
	
END COMPONENT;
begin 	
ip_40 : component PLL_40
  port map(
    refclk    => clk_ffly0_ref,
    locked    => lock_s,
    outclk_0  => clk_40,
    rst       => '0'
    );

ip_gen : component PLL_gen
  port map(
    refclk    => refclk_100,
    locked    => lock2_s,
    outclk_0  => clk_320,
    outclk_1  => clk_40s,
    rst       => '0'
    );

fmca_la_tx_p(3)    <= refclk_100;
fmca_la_tx_p(0)    <= clk_320;
fmca_la_tx_p(1)    <= clk_40s;
fmca_la_tx_p(2)    <= clk_40;


end architecture;