Quartus - altera_europa_support warnings

I'm not working for Altera ...

I just wanted to add that you will find a lot of warnings generated by Altera's IP and I personally find that a nuisance. Of course my own work doesn't cover all cases (as Altera's has to) but I strive to make my building blocks warning free, it saves a lot of unnecessary rereading the same warning over and over again ....

The warnings in this case are easily remedied as shown in the following code:

FUNCTION a_ext (arg : STD_LOGIC_VECTOR; size : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE arg_copy : STD_LOGIC_VECTOR ((arg'length - 1) DOWNTO 0) ;
VARIABLE result : STD_LOGIC_VECTOR((size-1) DOWNTO 0);
--VARIABLE i : integer := 0; 
VARIABLE bits_to_copy : integer ;
VARIABLE arg_length : integer ;
--VARIABLE LSB_bit : integer := 0;
BEGIN 
result  := (others => '0') ;
arg_copy := arg ;
arg_length := arg'length ;
bits_to_copy := a_min(arg_length, size);
FOR i IN 0 TO (bits_to_copy - 1) LOOP 
result(i) := arg_copy(i);
end LOOP;
RETURN(result); 
END;

You see that I moved the the assign from the variable declaration into the body of the function. With hindsight: they could have done without the most of the variables, i.e. only the variable 'result' is necessary. Furthermore the variable 'LSB_bit' is not used. Also there is no need to declare the loop variable (maybe it was in VHDL 87). It could have looked like this:

FUNCTION a_ext (arg : STD_LOGIC_VECTOR; size : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR((size-1) DOWNTO 0);
BEGIN 
result  := (others => '0') ;
FOR i IN 0 TO ( a_min(arg'length, size) - 1) LOOP 
result(i) := arg(i);
end LOOP;
RETURN(result); 
END;