Qsys

Hi - I have been struggling to use Qsys for my project having difficulty setting up an address bus. In my system I have an ALTGX instance configured as a transmitter/serializer and using 16bit data FIFO. It generates a data clock output which is 1/16th of the serial bit rate. I am trying to stream the data input into the FIFO from an on chip ROM memory. I use a 3bit counter clocked by the data clock to generate the LSB part of the memory address. (This arrangement cycles repeatedly through 8 memory locations which is a data set) In Qsys I define these lines as a conduit. Now I need another 5 address lines - the MSB part of the memory address - tied to input pins to select one of 32 sets of data.