Hi, also when i encounter problems?? For example i have a design which has worked perfect before on the Strativ IV dev kit and also on the Cyclone IV transceiver kit, both using the shared SSRAM and Flash on a tristate external bus. I do know that there are migration guidelines for the tristate bus, but whatever i do, i cannot get the design work anymore in reality... very annoying...
update: solved... see another thread that i posted
[BO] Adding your link so others can find it:
http://www.alteraforum.com/forum/showthread.php?p=119780#post119780