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Honored ContributorQsys reset connection problem in a Nios + DDR3 UniPHY system
Hello, all.
. For a while, I was able to avoid issues with the way that Qsys uses reset circuitry. I’m hitting a wall now, however (probably a silly thing I’m overlooking). Attached are screenshots of a (somewhat trivial) system. working_top.jpg and working_subsystem.jpg show a Qsys system that I can synthesize and fit in Quartus. After seeing that there are no setup/hold/recovery/removal violations, I test this system with Eclipse by using the ‘Memory Test Small’ template running as ‘Nios II Hardware’. . When adding more subsystems, I get to a point where I get recovery timing violations with the afi_clk. I attempted to solve this by adding a reset bridge to the DDR3 side as seen in nonworking_top.jpg. In doing so, however, I run into the popular problem (despite no listed setup/hold/recovery/removal violations) while downloading the program: . --------------------------------------------------------------------------------- Using cable “USB-Blaster [USB-0]”, device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused … Downloading ELF Process failed --------------------------------------------------------------------------------- . There’s some nuance I’m missing, an unintended consequence of placing the reset bridge on the DDR3 side of the system. I’m not quite sure how to fix this. Any help would be appreciated. . Other things that I have tried/could try in the future: . 1) Using the ‘Create Global Reset Network’ command in Qsys – This didn’t work, downloading the ELF Process failed. (it also breaks the working_top system in the same way if I use that there) . 2) I speculated that the Nios processor needs to come out of reset at the same time or later than the DDR3 circuitry and that this doesn’t happen because it takes time for the afi_clk to achieve lock. nonworking2_top.jpg shows this system. As suggested by the image name, downloading the ELF Process failed. . 3) I noticed that the Nios processor has the option to have cpu_resetrequest and cpu_resettaken signals. These conduits would need to be exported to the top level. Would manually interfacing with these signals be worthwhile?5 Replies
Altera_ForumI too would like to know the answer to some of those questions. I am currently struggling with the best/correct way to connect the resets and properly constrain my CycloneVGX qsys with nios, hard ddr3 and vip ip modules.
- Altera_Forum
It looks like you have a reset problem. Pay careful attention to how this system starts during power up - especially the NiOS -> DDR3 start-up.
Do you see the DDR3 INIT_DONE and READY states go active? If yes, then you'll need to sequence the reset of any component using the DDR3 to stay in reset while the DDR3 is initializing and de-assert when the DDR3 is ready. The avalon bus will stall if you try to access a device that isn't ready. One way to solve this is to use the DDR3 reset outputs as inputs to components using the DDR3. - Altera_Forum
Hello Everybody!
I think, that I have a similar problem. I worked on it the last two weeks but i did not succeed. The system (as you can see in the qsys file) works fine without the avalon bus (avl) of the ddr3 controller. As soon as the avalon bus (avl) of the ddr3 controller is connected to the data master, i get an error in eclipse "Connected system ID hash not found on target at expected base address." I really do not know what to do now. I almost tried everything. It would be very nice if you can help me. BR, Manuel - Altera_Forum
Hi manuel,
Dis you solve your problem? I have exactly the same problem right now :-( - Altera_Forum
I'm having the same trouble too. I'm using Quartus II v15, Nios2 with DDR2 and uClinux .
I have a watchdog timer on the outside of the Qsys block. I’ve tried resetting reset_n for 10us to 5 sec. Sometimes it will reboot sometimes it will not.
