Qsys reset connection problem in a Nios + DDR3 UniPHY system

It looks like you have a reset problem. Pay careful attention to how this system starts during power up - especially the NiOS -> DDR3 start-up.

Do you see the DDR3 INIT_DONE and READY states go active? If yes, then you'll need to sequence the reset of any component using the DDR3 to stay in reset while the DDR3 is initializing and de-assert when the DDR3 is ready. The avalon bus will stall if you try to access a device that isn't ready. One way to solve this is to use the DDR3 reset outputs as inputs to components using the DDR3.