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Altera_Forum
Honored Contributor
12 years agoI should mention that in Qsys, different cores have different data widths. The interconnexion between different widths is achieved by an Altera predefined element called Merlin Width Adapter. This element will simply not be synthesizable because it can only perform alignment between data widths within (16, 32, 64, 128, 256) at least as it seems to :)
You can check the source code for Merlin Width Adapter which appears to be written in system verilog and you will understand why you need a power of 2 data width.