Honored Contributor
Honored Contributor
i am trying to connect a 128-bit width master with 8-bit symbol of a clock crossing bridge to a 72-bit width slave with 9-bit symbol of qdrii+ sram controller. when connecting them, qsys gives an error message "error: system.: signal m0[8] and signal avl_r[9] must have the same symbol width." i cannot change the 9-bit symbol width of the qdrii+ controller. i also have to 8-bit symbol for the bridge because it's slave is also connected to avalon-mm master of pci-express interface. could you help me?
it is okay for me to connect only 64 bits from the 72 bits of the qdrii+ controller to make a symbol width 8 bits from 9 bits.
micky --- Quote End --- I remember I had to deal with something similar when trying to configure the controller for LPDDR2. I don't have much knowledge of the QDRII controller but I assume it is the same principle. The data width of the controller interface connected to qsys bus which is in your case 72 bit wide depends upon the data width of the external interface between the memory controller and QDRII PHY. Sometimes not all the Memory pins are connected to the FPGA device so you have to be careful how many pins you actually can use. I think at your level the best thing to do is to make a calculation of how much bandwidth you will need in order to identify how many external memory pins you can sacrifice. You might don't need to though in case you already have something like 16 bits wide interface. Try to change the width of the external bus (i think it can be done in the memory controller interface) so the internal width will be aligned with qsys interconnect. Change your memory control pins accordingly if there aren't done automatically.
