Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Qsys PCIe simulation in Active-HDL

I think the Qsys PCIe simulation export script for Aldec Active-HDL is broken. First, the default code for setting the QSYS_SIMDIR assumes that the execution directory is the same as the script directory, which isn't necessarily true. So I replaced 

set QSYS_SIMDIR "./../"]

with 

set QSYS_SIMDIR ] ".."]

And at least I can now compile. Now, however, I'm left with a bigger problem. When I try to elaborate using the 'elab' alias, I get told that I can't find altpciexpav_stif_rx. Probably other things too; that's just what stopped the elaboration.

There are dedicated encrypted Verilog modules in the mentor, cadence, and synopsis subdirectories, one of which is my missing altpciexpav_stif_rx. But nothing for Aldec, which means I can't elaborate, which means I'm up a creek.

Anyone gotten around this issue?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hello rgaddi,

    I don't know if you still try to work with Active HDL and PCIe in QSys. I run into the same problems as you did and was able to get around these problems with help from the altera support.

    You have to manually copy the Aldec specific files into your submodules directory. You can find this folder here: <INSTALL_DIR>/ip/altera/altera_pcie/altera_pcie_av_hip_avmm/aldec.

    Afterwards I had another problem because in the altera_pcie_bfm_components.v there were two modules called altpcietb_bfm_rpvar_64b_x8_pipen1b.v. I had to remove/comment one of these modules and then I was able to compile the whole project and elaborate.