QSYS output (synthesis) directory workaround?

Hello all,

I think Altera has finally seen some light and they have changed the approach in Qsys pro (not tried yet).

For those that still are looking for a work-around in qsys prime (vhdl):

1: create a wrapper component that instantiates your ip toplevel. Make sure to have the component definition in your architecture, direct instantiation does not work.

2: in qsys component editor, only add the wrapper file. should compile just fine

3: add the newly created component to your qsys system and generate.

4: manually create a qip file, listing all your component sources.

5: manually add this file to your project.

6: compile project.

If your work like this the wrapper file wil be copied to the synthesis directory and the other file remain on their original location. The wrapper file only changes when the entity changes and then you'll have to re-generate qsys system any way.

hope this helps.

Jo