Qsys now Platform designer, no error , error at same time, on wrong Avalon parameter.

Step to generate wrong model:

Add Avalon Slave signals ( here was QSYS default, my code was written on Quartus editor then assigned.)

Add byteenable after generating Conduit, then move to conduit ( this generated my mess with Qsys, probably selected by mistake then moved to conduit).

changed symbol width. wrong without byteselect, so it map twice to bus elements still 16 bit wide.

Address range look as it is ok

Build say nothing

Byteselect is still assigned to bus adapter. (found assigned as "11" (VHDL) or 2b'11 Verilog

VHDL generated look ok (My core was ok so took some time to point out)

Memory got duplicated from odd and even addresses, clearly no selection about byte was present and byte writing was destructive.