Qsys not generating same files in Simulation folder for VHDL vs Verilog?

This works fine here. If I create an empty Qsys with the SDRAM controller, select language "VHDL" and Generate the system, I am left with foo/simulation/submodules and foo/synthesis/submodules/ directories, both of which have identical copies of the Verilog instance of the controller.

I also have foo/simulation/foo.vhd with the top level.

Are you confusing the "foo/simulation" subdirectory with the top-level "simulation" directory? Qsys puts everything in a new subdirectory of the same name as your Qsys file. The "simulation" folder in your Quartus project directory is for e.g. the gate level / timing accurate simulation models generated as an output of the Quartus compilation.