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Altera_Forum
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9 years ago

Qsys not generating same files in Simulation folder for VHDL vs Verilog?

So I have wondered what is going on here and it seems there is a bug in the program. I am using Altera Quartus II 15.0 64 bit. I select SRAM/SSRAM controller from the IP catalog. Then I click gene...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

It looks like these are maybe components which are only generated in Verilog output. So when you say "VHDL" it is still generating Verilog output for these components. At least when I try, specifying VHDL, Qsys does generate .v file for the controller, same as if Verilog had been requested.

It may not be a bug, it may be deliberate that only Verilog language is supported for generating the file.