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Altera_Forum's avatar
Altera_Forum
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10 years ago

Qsys ip version inconsistency

I've been seeing what looks like an inconsistent behavior with qsys lately.

I have a design with a half dozen custom ip blocks as qsys modules. When I go through the procedure to update the hdl and update the component (manually bumping the version number), refreshing, and generating, things seem OK.

The results seem to be as I expect (the new IP block is used in the generation and the compiled results seem to be as expected).

But the odd behavior I see is that at times when I reopen the Qsys system, I get a warning about using the new IP block instead of the previous version (even though it seems that I was able to generate the system using the new version the last time I had qsys open).

This leads me to think that the qsys system isn't being saved properly (I have been trying to verify that the new version shows up in the qsys design prior to generation).

I'm second guessing myself a bit on this -- like I am missing a step or something, but it does not seem consistent.

Has anyone else seen this?

Lance

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi Lance,

    I am not sure about what the IP or Quartus version you are using but I am guessing that the new IP might have included some new warning messages. The new warning message from the Quartus could be some fix or some prevention where the user should be aware of, which is why there is a warning message. Just second guessing here as well :p
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Whoops, yes, I'm running quartus 15 update 2, I should have mentioned that.

    The warning is of the form "used ip_block_name version 2.025 instead of 2.024" -- where 2.025 is the version I had generated the system with and compiled the FPGA the last time I was working on it. The warning is really about the automatic IP updating that happens when you do a refresh or ask it to update all IP blocks. Very strange.

    I tend to update the hdl for a couple IP blocks, then go through the qsys component editor, ask it to analyze the hdl, fix any new interface/signal issues, give it a new revision number and then save. Once I have them updated in qsys and the connections made, I generate and move on.

    I had it happen to me again this evening. Very odd.

    Lance
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    After noticing a similar problem, I have come to the conclusion that I was not explicitly saving the qsys system each and every time after upgrading IP or editing parameters.

    I noticed some parameter edits were not saved and that caused me to come to this conclusion.

    So it would seem that it is pilot error, though I would consider it to be an inconsistent behavior of Qsys to not warn when closing/finishing when there are unsaved changes.

    Lance