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Altera_Forum's avatar
Altera_Forum
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10 years ago

Qsys ip version inconsistency

I've been seeing what looks like an inconsistent behavior with qsys lately. I have a design with a half dozen custom ip blocks as qsys modules. When I go through the procedure to update the h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Whoops, yes, I'm running quartus 15 update 2, I should have mentioned that.

The warning is of the form "used ip_block_name version 2.025 instead of 2.024" -- where 2.025 is the version I had generated the system with and compiled the FPGA the last time I was working on it. The warning is really about the automatic IP updating that happens when you do a refresh or ask it to update all IP blocks. Very strange.

I tend to update the hdl for a couple IP blocks, then go through the qsys component editor, ask it to analyze the hdl, fix any new interface/signal issues, give it a new revision number and then save. Once I have them updated in qsys and the connections made, I generate and move on.

I had it happen to me again this evening. Very odd.

Lance