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Altera_Forum's avatar
Altera_Forum
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8 years ago

Qsys Interconnect - force usage of "response" signal

Hi, the Avalon IP Specification refers to the response[1:0] signal as an optional signal. However there is complete silence in the rest of the document how to activate it. In my case I am using...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Made an SR to Altera and got the information the "response FIFO depth" has nothing to do with the response bus signal (completely undocumented IP parameter, name misleading, bad documentation on this one). The clock crossing bridge is not using the "response" signal at all.

Too bad, it would have been a good way to inform the Avalon master in one access cycle that a requested transaction was actually aborted and not successful.