Qsys Generation stops at classic module elaboration

I have recently installed Altera 12.0 suite on my computer. It is what my company has a license for. I have built an FPGA project for a Cyclone 4 using the Nios. I have added all my needed connections using Qsys. Then I went to generate my design in Qsys, but it stopped as shown below.

http://www.alteraforum.com/forum/attachment.php?attachmentid=9386&stc=1

The Qsys generation does not go past Starting classic module elaboration. In fact the only way to stop this is by using the task manager on my computer to end the process. I can either shut down Qsys or just stop perl.exe *32, which is using 25% of my CPU. If I do end the perl.exe process, the Qsys will freeze again at Running sopc_builder. I can then stop perl.exe *32 again which is using 25% of my CPU. Then the generation finishes with errors. Below is what is displayed from the Qsys generation.

Info: Running sopc_builder...

Info: StubCode: "BT8Nios" instantiated altera_avalon_onchip_memory2 "StubCode"

Error: Generation stopped, 290 or more modules remaining

Info: BT8Nios: Done BT8Nios" with 64 modules, 5 files, 1775747 bytes

Error: ip-generate failed with exit code 1: 2 Errors, 5 Warnings

Info: Finished: Create HDL design files for synthesis

I am asking for help on how to generate a design in Qsys. I have tried to start a project from scratch with just having a parallel pio and that still stopped. My coworker has a design that works on his machine, but the generation stops on mine. Does anybody what the problem could be? How can I fix this issue? I just need to get my project going. Thanks!