QSYS flattens our design hierarchy

@dave: I continued your suggestion, by putting hard paths in my .qip-file. E.g.

set_global_assignment -name VHDL_FILE -hdl_version VHDL_2008 -library UdpToFrame /SCM/FPGA/BuildingBlocksV2/IP/UdpToFrame/Source/Common_pkg.vhd

this seems to work, but GREATLY reduces flexibility of where we can check-out the files. A relative-path solution would be preferred....

In the code in your link you seem to refer to an environment variable ($::env(VHDL)). Would work, but isn't there a nicer way?

@anybody else then dave: your help is also appreciated ;)

Should I kick-off a change-request at Altera?