QSYS flattens our design hierarchy

Lets say I am generating a QSYS project "unsaved" with two IP blocks: TsToUdp and UdpToFrame.

The TsToUdp_hw.tcl has the line:

add_fileset_file ./TsToUdp/Common_pkg.vhd VHDL PATH Common_pkg.vhd

The UdpToFrame_hw.tcl has the line:

add_fileset_file ./UdpToFrame/Common_pkg.vhd VHDL PATH Common_pkg.vhd

these are different versions of the same package, so they have different contents!

But QSYS generates the file unsaved.qip with the following lines:

set_global_assignment -library "unsaved" -name VHDL_FILE 
set_global_assignment -library "unsaved" -name VHDL_FILE 

Thus both files are compiled into the same library, one overwriting the other! This will cause one of our IPs to fail during synthesis.

I would like QSYS to generate the following:

set_global_assignment -library "UdpToFrame" -name VHDL_FILE 
set_global_assignment -library "TsToUdp" -name VHDL_FILE