Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

QSYS feature-request: timing interface type

Hi all, given the version 15's interface-types, it is unnecessarily difficult to distribute control signals in a (nested) QSYS component and thus implement serial data processing. Streaming dat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thats valuable advice, thank you.

I decided to learn Verilog first when I began one year ago. Learned much about the concepts --- and the restrictions. Found that those restrictions can be partially lifted with generated HDL like from QSYS.

But I always wondered if really complex projects can be done with those concepts.

I also have a SystemVerilog-Book but did not dig into that until now.

I was not even aware of MyHDL, looks promising at first glance. I think I will have a closer look.

Regards, Andreas