QSYS feature-request: timing interface type

The pictures are a bit small to view, and I'd like to print them out to study your explanation further

The concept of streaming data is exactly that everything comes along with the data. In the case of the 'controller concept' you would only need output to input connections between the blocks, given that the 'controller' times it all? Maybe it would be easiest to design the loop-controller as a hand-coded component (in VHDL, Verilog or MyHDL) and not trying to coerce Qsys to do something it was not really meant for.