Forum Discussion
Altera_Forum
Honored Contributor
14 years agoOk. I think I figured out my detour into the unexpected 'regeneration' of the SOPC when I compile and sorry if this exposes the 'other flow' (perhaps it does not).
I had the .QSYS file listed among my project files. Being completely new to this QII stuff it seemed like a logical choice when my original design would not compile complaining it could not find the SOPC module to be instantiated in my top level verilog file. When I do that, the QSYS SOPC appears to be rebuilt each time I compile the design. Now I downloaded the recently update for v11 niosII_ethernet_standard_3c25 and noted that it does not have the .QSYS file listed in the project files but instead lists the ./<sopcname>/synthesis/<sopcname>.qip in the project files. And this being where the 'generate' step of the QSYS places the output files must have been what was suggested as the files to manually edit. So, having now learned lots about this tool, I will not add a .QSYS file to my project files unless I really want that behavior (which would be fine if it just worked!) I am reasonbly certain I have this figured out. Thanks for your patience and help. -dave