--- Quote Start ---
anyone would care to explain to me how my actual project could/can be simulated I would be greatly appreciative. If I am going about this the complete wrong way too, I would be most appreciative but really the goal is just to see if I can communicate over the avalon MM fabric with verilog. RAM is just being used because I figured it was the simplest block to test on.
--- Quote End ---
You want to look into the Avalon Verification Suite. You basically end up creating a stub Qsys system which exports all of your custom component ports, and then wrapping a testbench around it. You drive the Altera testbench components and it takes care of checking for any protocol violations (like whatever you're looking at right now).
http://www.altera.com/education/training/courses/oavl1100 http://www.altera.com/literature/ug/ug_avalon_verification_ip.pdf Section VII of the PDF has a tutorial.
Honored Contributor
