Altera_Forum
Honored Contributor
11 years agoQsys common bus
Hello!
I am sorry for my english. Help me solve a problem, please. I use Cyclone IV GX Transceiver Starter Kit Board. LCD, SSRAM and FLASH are connected to a common bus. Accordingly, some of the signals of LCD, SSRAM and FLASH are connected to one and the same pins of FPGA( example: LCD rs - pin A6, SSRAM address bus[0] - pin A6). I use LCD and SSRAM in my project. My project contains next components: 1. Nios processor; 2. Onchip_ram (tightly_coupled_memory); 3. Sysid; 4. Generic Tri-State Controller (for SSRAM); 5. Tri-State Conduit Bridge (for SSRAM); 6. Lcd controler 16x2; 7. Jtag; 8. Interval timer(sys_clk_timer); What other components should I add in my qsys project? What are components needed to work with multiple devices on the same bus? Thanks!