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Altera_Forum's avatar
Altera_Forum
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9 years ago

QSYS Clock Source block documentation is ambiguous

Hello all,

Does anyone know the correct answer to this issue I recently posted on the QSYS wiki.

Thanks!

clock source documentation is ambiguous

issue: Qsys Clock source component interface documentation is ambiguous. The interconnect clock source documentation indicates that reset synchronous edges might be none, both, or deassert. However the documentation doesn’t indicate if said synchronization is with respect to clock inputs to the block or clock outputs from the block. The user is left guessing about what these options cause to occur, and one of three possible scenarios. Perhaps synchronization must be guaranteed by user circuitry prior to the block inputs, is internally provided by the clock source block, or somehow magically is inserted by the QSYS compiler after the unsynchronized block outputs within the QSYS fabric. I suspect that most users assume that this synchronization is provided by the block or the QSYS fabric (the 2nd two scenarios), but after reading the Avalon interface specification I start to understand that the user must provide any synchronization specified in the clock input block externally to, and before any inputs to the clock source block (the 1st scenario).

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    It's basically related to both the input and output. If you have a clock source set to, say, "deassert", then it expects that the input reset signal will be synchronous to the clock when deasserted. It follows then that the output reset signal will also have the same characteristics.

    If you feed the reset input with a signal which does not have the same synchronisation (e.g. feeding a "both" input with a "deassert" signal), then a synchroniser will automatically be inserted - this is a big gotcha as it doesn't specifically say this, and suddenly you can find a large number of reset synchronisers all over the design.

    Basically a synchroniser is inserted in the following cases: 

    
 Required | Supplied
----------+----------
   Both   | Deassert
   Both   |   None
 Deassert |   None

    In all of the other cases, no synchroniser is inserted (nor required).

    If you are feeding in reset signals from outside Qsys, make sure they match the required characteristic/synchronisation setting as no reset synchroniser will be added for these.

    The best approach is to stick to just one type throughout unless you specifically require something different.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    What can be confusing, from my perspective, is that the documentation doesn’t make clear whether the specified synchronization is a contract that the input to the clock source block must satisfy, or if the specified synchronization is selecting the type of synchronization instantiated inside the clock source block. You appear to know that the former is the correct interpretation of the documentation.