QSYS Clock Source block documentation is ambiguous

It's basically related to both the input and output. If you have a clock source set to, say, "deassert", then it expects that the input reset signal will be synchronous to the clock when deasserted. It follows then that the output reset signal will also have the same characteristics.

If you feed the reset input with a signal which does not have the same synchronisation (e.g. feeding a "both" input with a "deassert" signal), then a synchroniser will automatically be inserted - this is a big gotcha as it doesn't specifically say this, and suddenly you can find a large number of reset synchronisers all over the design.

Basically a synchroniser is inserted in the following cases:

 Required | Supplied
----------+----------
   Both   | Deassert
   Both   |   None
 Deassert |   None

In all of the other cases, no synchroniser is inserted (nor required).

If you are feeding in reset signals from outside Qsys, make sure they match the required characteristic/synchronisation setting as no reset synchroniser will be added for these.

The best approach is to stick to just one type throughout unless you specifically require something different.