Qsys and tristate bridge

Hi Steve,

Yes, i will post a support request to Altera.

Although Altera intentionally did it this way to remain compatible with verilog it is quite unconvenient.

For example... some of the signals of the memory interfaces are not shared (for example the chip select lines). All the shared and unshared signals become available at the toplevel through the Tri-State conduit bridge.

The strange thing is that all the signals are then also defined as inout bidirectional signals. Sounds strange to me for output signals that are not shared.

Anyway.. it seems to be a synthesis issue which can only be discovered if you very thoroughly walk through the tremendous list of warnings. Then you will see that the synthesis tool connected these lines to GND.

regards!