Qsys and tristate bridge

Hi,

I found the following anomaly with Qsys:

I was trying to convert one of my SOPC designs to Qsys. Many of the Altera development kits have a shared SSRAM and Flash interface on a shared bus. When converting the SOPC design to Qsys, the tool converts all interfaces including a Tri State Conduit Bridge, Tri State Conduit Pin Sharer and the generic Tri State controllers.

Also, on the HDL example tab an example is generated for the (VHDL) instantiation of the Qsys system for usage in your toplevel.

For some weird reason signals that in fact are std_logic signals are shown as std_logic_vector with size 1.

The problem occurs when synthesizing the design. Although you could choose to interface to the pins of the FPGA as std_logic_vectors with size 1 (in fact a std_logic_vector(0 downto 0), it seems that the synthesis tools connects these toplevel pins to GND.

For my system this resulted in output enables, write enables and chip enables being tied to ground instead of proper connection to the wires of the Tri State Conduit Bridge.

The problem is probably caused by the fact that Qsys marks these signals as std_logic_vector(0 downto 0) while the corresponding generated Verilog code of the qsys system shows clearly single wire definitions.

I was able to solve this issue at the toplevel at the component instantiation of my qsys system by declaring these wires as std_logic.

This solver my problem and now the system runs ok again with SSRAM operating at 100+ MHz again..

Hope this info is useful for others