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Altera_Forum's avatar
Altera_Forum
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14 years ago

Qsys and SystemVerilog

Quick question:

Does Qsys not yet support SV multidimensional input/output ports for internal modules? I'm trying to construct a new Qsys component that makes use of SV style ports, but receive an error about unsupported features.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I am almost 100% that it doesn't support such feature. Same as VHDL records.