I'm running into the most frustrating issue with qsys.. I hope I'm missing some simple thing. The problem is I have a sysq-system and I use schematics as the top level so I create a symbol file of course from qsys and instantiate it at the top level.. Now, when I do some modification in the Qsys and regenerate and subsequently update the symbol then all pins get randomly changed to differnt locations in the symbol.. How can I fix this? It is most annoying to shuffle all pins again to the right pins. SOPC never did this before.

I use schematic based top level design, but noticed something similar with Qsys. The order of the inputs and outputs in the top level module generated by Qsys seems to be random. Not nearly as big a problem for me of course, but I was in the habit of comparing the top level sopc builder module to my source to make sure I wasn't missing any connections. Not nearly as easy to do now.

Yes, as I have DDR2 and video inputs/outputs it becomes quite a task to reshuffle all pins to their correct location after any qsys mods.. Altera, please fix this issue!

Unfortunately, not only that - seems that Qsys has a lot of schematic problems. First of all, there is no distinction between inputs and outputs anymore (?!?), unless you open up the symbol file (inputs are light blue, while outputs are purple). The "new and improved" interface has all the signals on one side, so it's pretty much impossible to distinct inputs from outputs. (SOPC 1, QSYS 0) Second, there is no distinction between lines and buses (?!?!?). When I use select tool which can be used to draw buses/lines once you're over the connection point, in Qsys it only draws lines, no buses. (SOPC 2, QSYS 0) Third, the complete symbol for Nios is a disaster - signals on one side only, all the lines/text inside the Nios symbol are overlapping, some text going out of the Nios symbol completely (usually signal names, but also some module names). The signal is completely different than all the other HDL symbols in our design. Good Altera, you've really made the distinction - all the other HDL symbols look great, while Nios looks terrible. Now it's really different, congrats. (SOPC 3, QSYS 0) Fourth, everytime I regenerate, the ports are randomized, as all of you guys noticed. (SOPC 4, QSYS 0) Fifth, anyone tried to edit the Nios symbol, so that it would look like something usable? It's impossible! Symbol editor has gone back ages from the previous versions of Quartus. (SOPC 5, QSYS 0) Sixth, address decoding for custom components is a mess. It was a bit hard in SOPC, well, now it doesn't work at all, thanks to the new merlin address router. (SOPC 6, QSYS 0) Productivity? Please, this is a joke. How can someone advertise a bad, buggy, unfinished product? And say it's better than SOPC? Increased productivity? :D They act like they never had a good product!

Unfortunately I run into those same issues as well... I was hoping very different kind of replies from this forum but seems like what I feared is quite true - for now at least.

Ok, I updated the wiki page with issues that I've encountered. As for me, I'll stick with the SOPC until Qsys becomes usable.

QSYS and symbols | Altera Community

14 Replies

Altera_Forum
Honored Contributor
14 years ago
I believe this problem has been fixed with Quartus v11.1
Altera_Forum
Honored Contributor
13 years ago
I just went through the threat. Unfortunately, I see the very same issues in the latest quartus 12.0 SP 2 version...
Altera_Forum
Honored Contributor
12 years ago
Some of us find the schematic way of showing system level interconnected blocks FAR SUPERIOR to that stupid text based HDL method of connecting things up. One glance with well named blocks and you have it. The new QSYS symbol generator is useless and seriously annoying. Altera - why did you not just maintain the status quo - it was not broken, and worked well. This one sided symbol completely wrecks the intelligence built into a good schematic. Please fix.
Altera_Forum
Honored Contributor
11 years ago
Nope that doesn't help at all. HDL files that tie together many large modules are very hard to understand. A block diagram is much better.

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QSYS and symbols

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