Qsys and basic signals

Hello.

So, i am change in top level:

-- onchip_mem : component hd_mem_onchip_mem

-- port map (

-- clk => onchip_mem_clk1_clk, -- clk1.clk

-- address => onchip_mem_s1_address, -- s1.address

-- clken => onchip_mem_s1_clken, -- .clken

-- chipselect => onchip_mem_s1_chipselect, -- .chipselect

-- write => onchip_mem_s1_write, -- .write

-- readdata => onchip_mem_s1_readdata, -- .readdata

-- writedata => onchip_mem_s1_writedata, -- .writedata

-- byteenable => onchip_mem_s1_byteenable, -- .byteenable

-- reset => onchip_mem_reset1_reset, -- reset1.reset

-- reset_req => '1' -- (terminated)

-- );

onchip_mem : hd_mem_onchip_mem

port map (

clk => clk,

address => address,

clken => clken,

chipselect =>chipselect,

write => write,

writedata => writedata,

byteenable => byteenable,

reset => reset,

reset_req => reset_req

);

And result similar, bus not driving.

From outside - i am not driving this signal and me very intresting what need add this is signal to top-level.

And about write data - yes i am have array from very slow process, now i am simply write data to register and now for expirience want accum. data to internal ram.

If posiible from you are side help - its be nice.

In all cases now - this simple project dont write any to on-chip.

Me need only one time understand this process.

Thank you for understand.