Qsys and basic signals

But you need to attach the signals from your process to the signals from the onchip ram - so:

onchip_mem : hd_mem_onchip_mem

port map (

clk => clk,

address => address,

clken => clken,

etc.

In your internal scope you are watching the onchip_mem signals, but nothing is driving them - hence they default to 1.

The onchip_mem signals you've got on your entity hd_mem, so they are coming in from outside the chip at the moment - do you have anything driving these?

You say in your original post that you want to write 2 bytes - where is the data you want to write coming from? This ultimately needs to connect to the writedata bus to your onchip memory.