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It takes A LOT OF ENERGY just to use the locked signal from a pll as a reset in a qsys system. I assume I have missed something and I'd like to know how you people are doing this stuff.
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Ha! Yes, I experienced the same frustration recently. My solution was to simply remove the PLL from the Qsys system and move it to the top-level of my design, i.e., my top-level HDL file instantiates the PLL, PLL locked synchronization and the Qsys system. The PLL clock and reset signal derived from the synchronized PLL locked signal were then the clock and input signal to the Qsys system.
The example design is in this thread:
http://www.alteraforum.com/forum/showthread.php?t=45927 Here's the top-level code:
-- ------------------------------------------------------------
-- PLL
-- ------------------------------------------------------------
--
u1: pll
port map (
areset => (not ext_rstN),
inclk0 => clkin_50MHz,
c0 => clk,
c1 => sdram_clk,
locked => pll_locked
);
-- ------------------------------------------------------------
-- Reset synchronizer
-- ------------------------------------------------------------
--
u2: sync
generic map (
RESET_STATE => '0',
PIPELINE => 2
)
port map (
clk => clk,
rstN => (ext_rstN and pll_locked),
d => '1',
q => rstN
);
-- ------------------------------------------------------------
-- Qsys system
-- ------------------------------------------------------------
--
u3: qsys_system
port map (
clk_clk => clk,
reset_reset_n => rstN,
sdram_cs_n => sdram_csN,
sdram_ras_n => sdram_rasN,
sdram_cas_n => sdram_casN,
sdram_we_n => sdram_weN,
sdram_cke => sdram_cke,
sdram_addr => sdram_addr,
sdram_ba => sdram_ba,
sdram_dqm => sdram_dqm,
sdram_dq => sdram_dq
);
Cheers,
Dave
Honored Contributor
