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Altera_Forum's avatar
Altera_Forum
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12 years ago

Qsys- BFM Testbench causing add_connection error

Hello- I'm having difficulties generating a testbench in Qsys. I have a system, comprised of a custom model, several altera stream test generator/checkers, and a few exported signals (among them, clock, reset, 3 register busses, and a custom conduit). I'm able to generate simulation and synthesis files, but after adding the UniPHY SDRAM DDR3 controller, I'm unable to generate the testbench necessary to fully test the system.

Despite having no problem generating simulation and synthesis files, I recieve a 
Error: add_connection tb_m08_s_inst_ss_reset_in_bfm.reset tb_m08_s_inst_m08_top_0_p_rx_ns_bfm.: No interface named tb_m08_s_inst_m08_top_0_p_rx_ns_bfm..
error when generating the testbench (Standard, BFM for standard Avalon Interfaces; simulation model is either none or verilog).

The custom conduit mentioned is the m08_top_0_p_rx_ns mentioned, and shouldn't be associated with the ss_reset mentioned (though they do share a commom clock).

Can anyone explain why it's happening/what's wrong, and just as importantly, how to fix it?

This is on Qsys 12.1sp1 Build 243, by the way. The custom component is in VHDL, and the simulation model is set to VHDL as well.

Thanks for taking a look!

bluefreq

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    A quick update- after contacting Altera support, I've confirmed that there's a problem with generating the interface for the Avalon-MM bridge, as well as the conduit (which wouldn't work under the 'generate standard Avalon interfaces' option in any case, apparently).

    An Altera representitive is looking into the issue, but the provided short-term work around was manually create the testbench system, manually adding master/slave BFMs.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I know this is an old thread, but I have had a similar issue with Quartus 14.0. Basically what I have found is if you try and export a conduit with an associated clock, but which doesn't have an associated reset, the testbench generation will fail. The solution (hack) is to associate a reset with the conduit even if you don't use it - add a dummy reset signal into the hdl file (if not there already) and add a reset (if not there already) to the _hw.tcl file to associate the conduit with. Then it will generate the testbench correctly.