QSys - Pin Planner won't accept PIN_W27 for PCIe Reset Input -Cyclone V GX DevelBoard

Hi,

I have a problem with the pin assignment using Altera’s Pin Planner.

I tried to set up a simple PCI express application with QSys and Quartus II. After set up the application, I would like to do the pin assignment for the FPGA. I am forced to use the Altera Cyclone V GX Development Board, because the Altera Cyclone V GT Development Board, which I have bought, was damaged.

The pin assignment, which is mentioned in the “Cyclone V GX FPGA Development Board – Reference Manual” is equal with the schematic from the Installation Kit (Quartus II 12.0.2.1 – downloaded yesterday).

PCIE_PERSTNW27LVTTL

PCIE_REFCLK_PW8HCSL

PCIE_REFCLK_NW7HCSL

PCIE_RX_P0AG21,5 V PCML

PCIE_RX_N0AG11,5 V PCML

PCIE_TX_P0AF41,5 V PCML

PCIE_TX_N0AF31,5 V PCML

After starting the synthesis, I get the following message:

“Error (16023): hard IP reset pin "PCI_RST" is assigned to illegal pin "PIN_W27". Change the pin assignment to pin "PIN_W24".”

It could be important to know, that Altera marked the Cyclone V GX Development Board as “deprecated”. Does anybody know why?

I have got the same problem with Altera’s PCI express example (“C:/altera/15.0/ip/altera/altera_pcie/altera_pcie_cv_hip_avmm/example_designs/ep_g1x1). It is possible to compile my PCI express application with the Pin Assignment of the Cyclone V GT board very well. I won’t change the PIN_W27 to PIN_W24 without knowing why. Furthermore, it is not possible to find the PCI express card within my Linux PCI tree with using PIN_W24. (I used the Cyclone IV GX Development Board before with the same host computer and it worked very well.)

Is there a mistake in altera’s documentation? (It is not listed inside the errata sheet)

Thanks for helping

Greeting

Thomas