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Honored Contributor
Honored ContributorQSYS - Errors on custom component
Hi,
I try to get my custom component to work under QSYS. It worked fine under SOPC . . . I get the following error messages from the custom component wizzard: Error: System.uart_0.clock_reset: Synchronous edges DEASSERT requires associated clock Error: System.uart_0.avalon: Interface must have an associated reset Error: System.uart_0.avalon: uart_0.avalon must declare an associated reset Error: System.uart_0.interrupt: uart_0.interrupt must declare an associated reset I have no idea what is wrong with my vhd file. The entity is declared as follows:
ENTITY uart IS
generic
(
GENERIC_RX_FIFO_SIZE : natural := 128;
GENERIC_TX_FIFO_SIZE : natural := 128;
GENERIC_INTENDED_FPGA_FAMILY : string := "Cyclone";
GENERIC_IMPLEMENT_FIFO_IN_MEMORY : string := "ON"
);
port
(
csi_clock_reset : IN STD_LOGIC;
csi_clock_clk : IN STD_LOGIC;
coe_uart_cts : IN STD_LOGIC;
coe_uart_rxd : IN STD_LOGIC;
avs_avalon_write : IN STD_LOGIC;
avs_avalon_read : IN STD_LOGIC;
avs_avalon_address : IN STD_LOGIC_VECTOR(3 downto 0);
avs_avalon_writedata : IN STD_LOGIC_VECTOR(31 downto 0);
coe_uart_txd : OUT STD_LOGIC;
coe_uart_rts : OUT STD_LOGIC;
ins_interrupt_irq : OUT STD_LOGIC;
avs_avalon_readdata : OUT STD_LOGIC_VECTOR(31 downto 0)
);
END uart;
