QSYS - Errors on custom component

You shouldn't have to change anything in your HDL, the missing clock assignments are just a problem with the .tcl file. When you were creating the interface definitions in component editor did you remember to assign the clock interface to all your slave, reset, and interrupt ports? Also I just noticed the association of the interrupt interface is missing (you need to associate it to the slave port). If you were expecting the tools to do this automatically then that might explain why you ran into this (the tools don't know what your intentions are so you need to do that manually).