Honored Contributor
Honored ContributorHi BadOmen,
you are right, I did not assigne the clock interface to my reset port. I think I haacvn't done that beause I never did that in SOPC. I think I have to update and deepen my understanding of the SOPC/QSYS custom component creation process. My current problem right now is, that one of my own I2C components does not go throught bthe component editor because it does not provide a reset input. I think I can solve this problem by just providing one but I had no problems in SOPC with that entity definition. Is there some kind of change documentation between QSYS and SOPC so that I can see what is newly required by QSYS? What is your suggested way of getting started with QSYS? It seems that I have to start from page one of the QSYS documentation because I guess there are many new features and rules that I have to know of instead of doing it the trial and error way. . . Why, for example, is it mandatory to define a reset interface port? I thought it is the descision of the designer if he needs a reset, or not? Also, why does the component editor have to know if the reset is associated with the clock? I mean, in the past (in SOPC) it seemed, that the designer was responsible to define in the architecture (in VHDL) the handling of the interface signals. Why has that changed? Or am I thinking in the wrong direction, here? Thanks, Maik
